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IW4017B
Description
The IW4017B is 5 -stageJohnson counter having 10 decode outputs. shaping that allows unlimited clock input pulse rise and fall times. The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBITsignal is low. Counter advancement via the clock line isinhibited when the CLOCK INHIBIT signal is high. A high RESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits highspeed operation, 2- input decode-gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counting sequence. The decoded Outputs are normally low and go high only at their C ARR YOUT Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse
respective decoded time slot. Each decoded output remains high for one full clock cycle. A Signal completes one cycle every 10 clock input cycles.
Features
Operating Voltage Range: 3.0 to 18 V at 18 V over full packageMaximum input current of 1 u A temperature range ;100 nA at 18 V and 25 C Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply
Pin Assignment
16 DIP - 16
16 SOP - 16
Logic Diagram Function Table
Clock L X X Clock Enable X H X Reset Output State L L H
Package
L X X H PIN16 = VCC PIN 8 = GND
L L L L
no change no change reset counter Q0=H, Q1-Q9=L, C0=H Advance to next state no change no change Advance to next state
Carry Out=H for Q0 ,Q1,Q2,Q3 or Q4=H Carry Out = L otherwise, X = don ' t care
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IW4017B
Absolute Maximum Ratings
Symbol VCC V IN VOUT IIN PD PD Tstg TL Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP Value -0.5 to 20 -0.5 to VCC 0.5 -0.5 to VCC 0.5 + 10 750 500 100 -65 to 150 260 Unit V V V mA mW mW C C
SOIC Package Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating - Plastic DIP: - 10 mW/ from 65to 125 C C SOIC Package from 65 125 C to C
Recommended Operating Conditions
Symbol VCC VIN , VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min 3.0 0 -55 Max 18 VCC 125 Unit V V C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V IN and V OUT should be constrained to the range GND (VIN or VOUT) VCC . Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC Unused outputs must be left open.
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IW4017B
DC Electrical Characteristics
VCC Symbol 125 VIH Parameter Test Conditions V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 18 5.0 10 15 20 5.0 10 15 5.0 5.0 10 15 (Voltages Referenced to GND) Guaranteed Limit -55 C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 4.5 9.0 13.5 0.05 0.05 0.05 0.5 1.0 1.5 + 0.1 1.0 2.0 4.0 20 0.64 1.6 4.2 -0.64 - 2.0 - 1.8 - 4.2 25 C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 4.5 9.0 13.5 0.05 0.05 0.05 0.5 1.0 1.5 + 0.1 1.0 2.0 4.0 20 0.51 1.3 3.4 -0.51 - 1.6 - 1.3 - 3.4 C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 4.5 9.0 13.5 0.05 0.05 0.05 0.5 1.0 1.5 + 1.0 30 60 120 600 0.36 0.9 2.4 mA -0.36 - 1.15 - 0.9 - 2.4 Unit V
Minimum High-Level VOUT=0.5 V or VCC - 0.5 V Input Voltage VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or V - 1.5 V CC Maximum Low Level Input Voltage VOUT=0.5 V or VCC - 0.5 V VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or V - 1.5 V CC
VIL
V
VOH
Minimum High-Level VIN=GND or VCC Output Voltage VIL =1.5V, VIH=3.5V, IO=-1A VIL =3.0V, VIH=7.0V, IO=-1A VIL =4.0V, VIH=11V, IO=-1 A
V
VOL
Maximum Low-Level Output Voltage
VIN=GND or VCC
V
VIL =1.5V, VIH=3.5V, IO=1 A VIL =3.0V, VIH=7.0V, IO=1 A VIL =4.0V, VIH=11V, IO=1 A IIN Maximum Input Leakage Current VIN= GND or VCC VIN= GND or VCC
uA uA
ICC Maximum Quiescent Supply Current (per Package) I Minimum Output Low (Sink) Current
VIN= GND or VCC VOL=0.4 V VOL=0.5 V VOL=1.5 V VIN= GND or VCC VOH=4.6 V VOH=2.5 V VOH=9.5 V VOH=13.5 V
mA
IOH
Minimum Output High (Source) Current
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IW4017B
AC Electrical Characteristics
Symbol fmax Parameter Maximum Clock Frequency (C L =50pF, RL =200 k , Input t r =t f =20 ns) VCC Guaranteed Limit V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 -55 C 2.5 5 5.5 650 270 170 600 250 160 200 100 80 530 230 170 25 C 2.5 5 5.5 650 270 170 600 250 160 200 100 80 530 230 170 5 125 C 2.0 4.0 5.0 800 350 250 750 300 200 300 150 120 700 300 250 Unit MHz
tPLH, tPHL MaximumPropagation Delay, Clock to Decode Output (Figure 1) tPLH, tPHL Maximum Propagation Delay, Clock to Carry Output (Figure 1) Maximum Output Transition Time, Carry Output or Decode Output (Figure 1) Maximum Propagation Delay, Reset to Output or Decode Output (Figure 1) CIN Maximum Input Capacitance
ns
ns
tTLH, tTHL
ns
tPLH, tPHL Carry
ns
pF
Timing Requirements
Symbol tw Parameter
(VCC=5.0V + 10%, CL =50pF, RL =200 k ns) V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 260 110 60 400 280 150 230 100 70 -55 C 200 90 60 25 C 200 90 60
, Input t r =t f =20 125 C 300 150 100
Unit ns
Minimum Pulse Width, Clock (Figure 1)
tr, tf
Maximum Input Rise and Fall Times, Clock (Figure 1) Minimum Pulse Width, Reset (Figure 1)
UNLIMITED 260 110 60 400 280 150 230 100 70 400 180 100 550 400 200 300 150 100
ms
tw
ns
trem
Minimum Removal Time, Reset (Figure 1)
ns
tSU
Minimum Setup Time, Clock Inhibit to Clock (Figure 1)
ns
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IW4017B
1/ f s u t 50% t f CLOCK INHIBI T 50% tw RESET t PL t PH L H 50% T t PH DECODE L t PL H 50%
THL
max 90 90 50% 50% 10 10 t r 50 50%
tw V CC %% 50% % t rem V CC GN D V CC 50% 50% GN D V CC GN D 90% 10% 50% t THL V CC GN D %% GN D
CLOCK
Q1
DECODE Q9 OUTPU
50%
90% CARRY OUTPU T 10%
Q0 OR
Figure 1. Switching Waveforms
Timing diagram
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IW4017B
Expanded Logic Diagram
Address :
Postalcode:100039 Tel: 86-010-58895780 / 81 / 82 / 83 / 84 Http://www.estek.com.cn Email:sales@estek.com.cn
6A06--6A07 Rm 6A07,Changyin Office Building ,No.88,Yong Ding Road,Hai Dian District ,Beijing
Fax : 010-58895793
REV No:01-060833
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